The NTSC standard for television defines a composite video signal. The composite video signal has a fixed vertical resolution of 525 horizontal lines, with 59.94 fields displayed per second. Even and odd fields are displayed sequentially, interlacing the full frame. One full frame is made of two interlaced fields, and is displayed about every 1/30 of a second. A composite sync signal may be derived from the NTSC composite video signal by performing functions such as clipping and buffering on the composite video signal. There may be several commercially available integrated circuits for generating a composite sync signal from a composite video signal, including the LM1881 from National Semiconductor Corporation.
The composite sync signal includes a horizontal sync region with a period of about 63.5 μs. During a vertical blanking interval, the composite sync signal still includes the horizontal sync pulses with a period of about 63.5 μs. However, during the vertical blanking period, equalizing pulses are interleaved with the horizontal sync pulses. The equalizing pulses have a period of about 63.5 μs, and lag behind the horizontal sync pulses by about 31.75 μs (or 31.8 μs, rounding to three significant digits). Accordingly, the period of the NTSC composite sync signal is approximately 31.8 μs during the vertical blanking period. However, this increased frequency NTSC signal when equalizing pulses occur may be problematic if a phase-locked loop (PLL) is employed for horizontal deflection.
PLL applications typically provide an output clock signal by comparing the output clock signal to a reference clock signal. A phase-frequency detector (PFD) circuit is often employed to provide a raw control signal to a loop filter. The phase-frequency detector circuit provides the raw control signal in response to comparing the phase and frequency of the output clock signal to the reference clock signal. The loop filter often is a low-pass filter (LPF) that is arranged to provide a smoothed or averaged control signal in response to raw control signal. Typically, a voltage-controlled oscillator (VCO) is arranged to receive the control signal from the loop filter. The VCO produces the clock signal in response to the control signal such that the frequency of the clock is varied until the phase and frequency of the clock signal are matched to the reference clock signal.
A PLL circuit may include a PFD circuit that provides UP and DOWN signals in response to the comparison between the output clock signal and the reference clock signal. The UP and DOWN signals are dependent on both the phase and frequency of the output and reference clock signals. The UP signal is active when the frequency of the output clock signal is lower than the reference signal, while the DOWN signal is active when the frequency of the output clock signal is determined to be higher than the reference signal. Similarly, the UP signal is active when the phase of the output clock is lagging behind the phase of the reference clock, and the DOWN signal is active when the phase of the output clock is leading the phase of the reference clock.